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nt3881d dot matrix lcd controller and driver 1 v2.4 features internal lcd drivers 16 common signal drivers 40 segment signal drivers (can be externally extended to 400 segments using nt3882) maximum display dimensions 40 characters * 2 lines or 80 characters * 1 line interfaces with 4-bit or 8-bit mpu versatile display functions provided on chip: display clear, cursor home, display on/off, cursor on/off, character blinking, cursor shift, and display shift three duty factors, selected by program: 1/8, 11/11, and 1/16 displays data ram (dd ram): 80 x 8 bits (displays up to 80 characters) character generator ram (cg ram): 64 x 8 bits for general data, 8 5 x 8 programmable dot patterns, or 4 5 x 10 programmable dot patterns low voltage reset novatek identification code bonding option for a-type and b-type waveform character generator rom (cg rom): 3 kinds of cg rom sizes: 192 characters: 160 5 x 8 dot patterns 32 5 x 10 dot patterns 240 characters: 192 5 x 8 dot patterns 48 5 x 10 dot patterns 256 characters: 192 5 x 8 dot patterns 64 5 x 10 dot patterns custom cg rom is also available built-in power-on reset function logic power supply: single +5v supply lcd driver power supply: v 1 - v 5 (v dd +0.3 - v dd -13.5) three oscillator operations (freq. = 250khz - 270khz): ? internal oscillation ? ceramic resonator ? external clock cmos process available in 80-pin qfp or in chip form general description the nt3881d is a dot matrix lcd controller and driver lsi that can operate with either a 4-bit or an 8-bit microprocessor (mpu). nt3881d receives control character codes from the mpu, stores them in an internal ram (up to 80 characters), transforms each character code into a 5 x 7, 5 x 8, or 5 x 10 dot matrix character pattern, and then displays the codes on the lcd panel. the built-in character generator rom consists of 256 different character patterns. the nt3881d also contains character generator ram where the user can store 8 di fferent character patterns at run time. these memory features make character display flexible. nt3881d also provides many display instructions to achieve versatile lcd display functions. the nt3881d is fabricated on a single lsi chip using the cmos process, resulting in very low power requirements. with several nt3882 driver ics connected to the nt3881d, up to 80 characters can be displayed.
nt3881d 2 v2.4 pin configuration um3881df nt3881df s e g 2 1 s e g 2 0 s e g 1 9 s e g 1 8 s e g 1 7 s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 g n d o s c 1 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 db1 db0 e r/w rs d m vdd cl2 cl1 v5 v4 v3 v2 v1 osc2 s e g 2 2 s e g 3 9 s e g 4 0 c o m 1 6 c o m 1 5 c o m 1 4 c o m 1 3 c o m 1 2 c o m 1 1 c o m 1 0 c o m 9 c o m 8 c o m 7 c o m 6 c o m 5 c o m 4 c o m 3 c o m 2 c o m 1 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
nt3881d 3 v2.4 pad configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 81 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 nt3881dh 66 33 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 gnd osc1 seg39 seg40 com1 6 com1 5 com1 4 com1 3 com1 2 com1 1 com1 0 com9 com8 com7 com6 com5 com4 com3 com2 com1 db7 db6 db5 db4 db3 db2 o s c 2 v 1 v 2 v 3 v 4 v 5 c l 1 c l 2 v d d a m d r s r / w e d b 0 d b 1 v d d b s e g 2 3 s e g 2 4 s e g 2 5 s e g 2 6 s e g 2 7 s e g 2 8 s e g 2 9 s e g 3 0 s e g 3 1 s e g 3 2 s e g 3 3 s e g 3 4 s e g 3 5 s e g 3 6 s e g 3 7 s e g 3 8
nt3881d 4 v2.4 block diagram i/o butter instruction register (ir) address counter timing generator instruction decoder cur50r address courter display data ram (dd ram) 80 x 8 bits busy flag (bf) data register (dr) 7 8 cursor /blink controller 16-bit shift register common signal driver character generator ram (cg ram) 64 x 8 bits character generator rom (cg rom) 40-bit latch circuit segment signal driver parallel-to-serial converter 40-bit shift register 7 5 5 7 8 8 40 db7~db4 4 4 db3~db0 40 16 m cl1 cl2 com1 | com16 seg1 | seg40 d osc2 8 rs r/w e 8 v1 v2 v3 v4 v5 osc1 gnd vdd 7 7 7 7 8 3 16
nt3881d 5 v2.4 pin and pad descriptions pin and pad no. designation i/o external connection description 1 - 22 seg22 - seg1 o lcd panel segment signal output pins 24, 25 osc1, osc2 pins connected to resistor or ceramic filter for internal clock oscillation. for external clock operation, clock inputs to osc1. 26 - 30 v 1 - v 5 p power supply power supply for lcd driver 31 cl1 o nt3882 clock to latch serial data d sent to nt3882. 32 cl2 o nt3882 clock to shift serial data d 33, 81 vddb, vdda p power supply v dd : +5v a-type waveform: v dd bond to vdda b-type waveform: v dd bond to vddb 23 gnd p power supply gnd: 0v 34 m o nt3882 switch signal to convert lcd drive waveform to ac 35 d o nt3882 character pattern data corresponding to each common signal is transmitted serially from this output. 0-non select ion, 1-selection. 36 rs i mpu register select signal 0: instruction register (write) busy flag, address counter (read) 1: data register (write, read) 37 r/w i mpu read/write control signal 0: write 1: read 38 e i mpu read/write start signal 39 - 42 db0 - db3 i/o mpu lower 4 tri-state bi-directional data bus for transmitting data between mpu and nt3881d. not used during 4-bit operation. 43 - 46 db4 - db7 i/o mpu higher 4 tri- state bi-directional data bus for transmitting data between mpu and nt3881d. db7 is also used as busy flag. 47 - 62 com1 - com16 o lcd panel common signal output pins 63 - 80 seg40 - seg23 o lcd panel segment signal output pins
nt3881d 6 v2.4 functional description the nt3881d is a dot-matrix lcd controller and driver lsi. it operates with either a 4-bit or an 8-bit microprocessor (mpu). the nt3881d receives both instructions and data from the mpu. some instructions set operation modes, such as the function mode, data entry mode, and display mode; as well as some control lcd display functions, such as clear display, restore display, shift display, and cursor. other instructions include read and write both data and addresses. all instructions allow users convenient and powerful functions to control the lcd dot-matrix displays. data is written into and read from the data display ram (dd ram) or the character generator ram (cg ram). as display character codes, the data stored in the dd ram decodes a set of dot-matrix character patterns that are built into the character generator rom (cg rom). the cg rom, with many character patterns (up to 256 patterns), defines the character pattern fonts. the nt3881d regularly scans the character patterns through the segment drivers. the cg ram stores character pattern fonts at run time if users intend to show character patterns that are not defined in the cg rom. this feature makes character display flexible. other unused bytes can be used as general-purpose data storage. the lcd driver circuit consists of 16 common signal drivers and 40 segment signal drivers allowing a variety of application configurations to be implemented. additionally, the user can extend display size by cascading the segment driver lsi nt3882. the maximum display dimensions can be either 80 characters in a 1-line display or 40 characters in a 2-line display. character generator rom (cg rom) the character generator rom generates lcd dot character patterns from the 8- bit character pattern codes. the nt3881d provides 3 cg rom configurations: 1. 192 characters: the cg rom contains 160 5 x 8 dot character patterns and 32 5 x 10 dot character patterns. an example is the nt3881d-01, in which the relation between the character codes and character patterns is shown in table 1. the character codes from 00h to 0fh are used to get character patterns from the cg ram. character codes from 10h to 1fh and from 80h to 9fh map to full character patterns. character codes from e0h to ffh are assigned to generate 5 x 10 dot character patterns, and other codes are used to generate 5x8 dot character patterns. 2. 240 characters: the cg rom contains 192 5 x 8 dot character patterns and 48 5 x 10 dot character patterns. an example of this type is the nt3881d-02, in which the relation between the character codes and character patterns is shown in table 2. the character codes from 00h to 0fh are used to get character patterns from the cg ram. character codes from 10h to 1fh and from e0h to ffh are assigned to generate 5 x 10 dot character patterns, and other codes to generate 5 x 8 dot character patterns. no null character pattern exists in this type. note that the underlined cursor, displayed on the 8th duty may be obscure if the 8th row of a dot character pattern is coded. we recommend that users display the cursor in the blinking mode if they code 5x8 dot character patterns is their custom cg rom. 3. 256 characters: the cg rom contains 192 5 x 8 dot character patterns and 64 5 x 10 dot character patterns. no adequate example is presented here. the only difference between this type and the just mentioned second type is that the character codes from 00h to 0fh get character patterns from the cg rom rather than from the cg ra m. these character codes are assigned to generate 5 x 10 dot character patterns. in this application, the cg ram would be employed as a general-purpose data storage. custom character patterns are available by mask- programming rom. for convenience of character pattern development, novatek has developed a user-friendly editor program for the nt3881d to help determine the character patterns users prefer. by executing the program on the computer, users can easily create and modify their character patterns. by transferring the resulting files generated by the program through a modem or some other communication method, the user and novatek have established a reliable, fast link for programming the cg rom.
nt3881d 7 v2.4 absolute maximum ratings* power supply voltage (v dd ) . . . . . . . . . . -0.3v to +0.7v power supply voltage(v 1 tov 5 ).v dd -13.5v to v dd +0.3v input voltage (v i ) . . . . . . . . . . . . . . . -0.3v to v dd +0.3v operating temperature (t opr ) . . . . . . . . -20 c to +75 c storage temperature (t stg ) . . . . . . . -55 c to +125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. all voltage values are referenced to gnd = 0v v 1 to v 5 , must maintain v dd v 1 v 2 v 3 v 4 v 5 . dc electrical characteristics (v dd = 5.0v, gnd = v ee = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions applicable pin v ih1 "h" level input voltage (1) 2.2 - v dd v db0 - db7, rs, v il1 "l" level input voltage (1) -0.3 - 0.8 v r/w, e v ih2 "h" level input voltage (2) v dd -1.0 - v dd v osc1 v il2 "l" level input voltage (2) gnd - 1.0 v v oh1 "h" level output voltage (1) 2.4 - - v i oh = -0.25ma db0 - db7 v ol1 "l" level output voltage (1) - - 0.4 v i ol = 1.2ma (ttl) v oh2 "h" level output voltage (2) 0.9 v dd - - v i oh = -0.04ma cl1, cl2, m, d v ol2 "l" level output voltage (2) - - 0.1 v dd v i ol = 0.04ma (cmos) v com driver voltage descending (com) - - 2.9 v i d = 0.05ma com1 - 16 v seg driver voltage descending (seg) - - 3.8 v i d = 0.05ma seg1 - 40 i il input leakage current -1 - 1 a v in = 0 to v dd -i p pull-up mos current 50 125 250 a v dd = 5v rs, r/w, db0-db7 i op supply current power supply current - 0.3 0.5 ma rf oscillation, from external clock v dd =5v, f osc = f cp = 270khz v dd
nt3881d 8 v2.4 dc electrical character (continued) symbol parameter min. typ. max. unit conditions applicable pin external clock operation f cp external clock operating frequency 125 270 350 khz t duty external clock duty cycle 45 50 55 % t rcp external clock rise time 0.1 - 0.5 s t fcp external clock fall time 0.1 - 0.5 s internal clock operation (rc oscillator) f osc oscillator frequency 190 270 350 khz rf = 91k ? 2% internal clock operation (ceramic resonator oscillator) f osc oscillator frequency 245 250 255 khz ceramic resonator v lcd1 v lcd2 lcd driving voltage 4.6 3.0 - v dd v v dd - v 5 1/5 bias 1/4bias ac characteristics read cycle (vdd = 5.0v, gnd = vee = 0v, ta = 25 c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 1 t whe enable "h" level pulse width 300 - - ns figure 1 t re , t fe enable rise/fall time - - 25 ns figure 1 60 1 t as rs, r/w setup time 100 2 - - ns figure 1 t ah rs, r/w address hold time 10 - - ns figure 1 t rd read data output delay - - 190 ns figure 1 t dhr read data hold time 20 - - ns figure 1
nt3881d 9 v2.4 ac characteristics (continued) write cycle (v dd = 5.0v, gnd = v ee = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 2 t whe enable "h" level pulse width 300 - - ns figure 2 t re , t fe enable rise/fall time - - 25 ns figure 2 60 1 t as rs, r/w setup time 100 2 - - ns figure 2 t ah rs, r/w address hold time 10 - - ns figure 2 t ds data output delay 100 - - ns figure 2 t dhr data hold time 10 - - ns figure 2 notes: 1: 8-bit operation mode 2: 4-bit operation mode timing characteristics of interface signals with segment driver lsi nt3882 (v dd = 5v, gnd = v ee = 0v, t a = 25 c) symbol parameter min. typ. max. unit conditions t cwh clock pulse width high 800 - - ns figure 3 t cwl clock pulse width low 800 - - ns figure 3 t su data setup time 300 - - ns figure 3 t dh data hold time 300 - - ns figure 3 t csu clock setup time 500 - - ns figure 3 t dm m delay time -1000 - 1000 ns figure 3 power supply conditions using internal reset circuit symbol parameter min. typ. max. unit conditions t ron power supply rise time 0.1 - 10 ns figure 4 t off power supply off time 1 - - ms figure 4
nt3881d 10 v2.4 timing waveforms read operation rs r/w e db0~db7 v ih1 v il1 v ih1 v il1 v ih1 v il1 v il1 v ih1 v il1 v il1 v ih1 vald data t dhr t ah t fe t wem t re v ih1 v il1 t as t ah t rd t cyce figure 1. bus read operation sequence (reading out data from nt3881d to mpu) write operation rs r/w e db0 ~ db7 v ih1 v il1 v ih1 v il1 v il1 v il1 v ih1 v il1 v il1 v ih1 vald data t dhw t ah t fe t wem t re v ih1 v il1 t as t ah v ih1 v il1 v il1 t ds t cyce figure 2. bus write operation sequence (writing data from mpu to nt3881d)
nt3881d 11 v2.4 timing waveforms (continued) interface signals with segment driver lsi 0.9 v dd 0.9 v dd 0.1 v dd 0.9 v dd t cwh t cwh t csu 0.9 v dd 0.1 v dd t cwl t dh t su 0.9 v dd 0.1 v dd 0.1 v dd clk1 clk2 d 0.9 v dd 0.1 v dd 0.1 v dd t dm m t csu figure 3. sending data to segment driver lsi nt3882 interface signals with segment driver lsi (continued) 0.2v 0.2v 0.2v 4.5v v dd t ron t off t off > 1ms 0.1ms > t ron > 10ms figure 4. t off stipulates the time of power off for instantaneous power supply to or when power supply repeats on and off. note 1: the nt3881d has three clock options: a. internal oscillator operation (with ceramic filter) ceramic filter osc1 osc2 c1 c2 rf : 1m ? 10% rd : 3.3k ? 5% c1 = c2 : 680pf 10%
nt3881d 12 v2.4 b. internal oscillator (with rf resistor) osc1 osc2 rf: 91kohm + 2% only rf may be connected between osc1 and osc2. the wire connection rf must be as short as possible. c. external clock operation osc1 osc2 pulse input osc1 and osc2. note 2 : input/output terminals: a. input terminal applicable terminal : e (no pull up mos) pmos nmos v dd applicable terminals: rs, r/w (with pull up mos) pull up mos nmos pmos v dd pmos v dd
nt3881d 13 v2.4 b. output terminal applicable terminals: cl1, cl2, m, d pmos nmos v dd c. i/o terminal applicable terminals: db0 to db7 pull up mos nmos pmos v dd pmos v dd v dd enable pmos nmos data (output circuit) (tristate)
nt3881d 14 v2.4 table 1. correspondence between character codes and character patterns (novatek standard nt3881d-01)
nt3881d 15 v2.4 table 2. correspondence between character codes and character patterns (novatek standard nt3881d-02)
nt3881d 16 v2.4 instruction set instruction code function execution time (max) rs rw db7 db6 db5 db4 db3 db2 db1 db0 (f osc = 250khz) display clear 0 0 0 0 0 0 0 0 0 1 clear entire display area, restore display from shift, and load address counter with dd ram address 00h. 1.64ms display/ cursor home 0 0 0 0 0 0 0 0 1 * restore display from shift and load address counter with dd ram address 00h. 1.64ms entry mode set 0 0 0 0 0 0 0 1 i/d s specify direction of cursor movement and display shift mode. this operation takes place after each data transfer (read/write). 40 s display on/off 0 0 0 0 0 0 1 d c b specify activation of display (d) cursor (c) and blinking of character at cursor position (b). 40 s display/ cursor shift 0 0 0 0 0 1 s/c r/l * * shift display or move cursor. 40 s function set 0 0 0 0 1 dl n f * * set interface data length (dl), number of display line (n), and character font (f). 40 s ram address set 0 0 0 1 acg load the address counter with a cg ram address. subsequent data access is for cg ram data. 40 s dd ram address set 0 0 1 add load the address counter with a dd ram address. subsequent data access is for dd ram data. 40 s busy flag/ address counter read 0 1 bf ac read busy flag (bf) and contents of address counter (ac). 0 s cg ram/ dd ram data write 1 0 write data write data to cg ram or dd ram. 40 s cg ram/ dd ram data read 1 1 read data read data from cg ram or dd ram. 40 s note 1: symbol "*" signifies an insignificant bit (disregard). note 2: correct input value for "n" is predetermined for each model.
nt3881d 17 v2.4 instruction set (continued) instruction code function execution time (max) rs rw db7 db6 db5 db4 db3 db2 db1 db0 (f osc = 250khz) i/d = 1 : increment i/d = 0 : decrement s = 1 : display shift on d = 1 : display on c = 1 : cursor display on b = 1 : cursor blink on s/c = 1 : shift display s/c = 0 : move cursor r/l = 1 : shift right r/l = 0 : shift left dl = 1 : 8-bit dl = 0 : 4-bit n = 1 : dual line n = 0 : signal line f = 1 : 5x10 dots f = 0 : 5x8 dots bf = 1 : internal operation bf = 0 : ready for instruction dd ram : display data ram cg ram : character generator ram acg : character generator ram address add : display data ram address ac : address counter note 1: symbol "*" signifies an insignificant bit (disregard). note 2: correct input value for "n" is predetermined for each model.
nt3881d 18 v2.4 interface to lcd (1) character font and number of lines the nt3881d provides a 5 x 7 dot character font 1-line mode, a 5 x 10 dot character font 1-line mode and a 5 x 7 dot character font 2-line mode, as shown in the table below. three types of common signals are available as displayed in the table. the number of lines and the font type can be selected by the program. number of lines character font number of common signals duty factor 1 5 x 7 dots + cursor (or 5x8 dots) 8 1/8 1 5 x 10 dots + cursor 11 1/11 2 5 x 7 dots + cursor (or 5x8 dots) 16 1/16 (2) connection to lcd the following 4 lcd connection examples show the various combinations between characters and lines. nt3881d can directly drive the following combinations: (a) 5 x 8 font - 8 character x 1 line (1/8 duty cycle, 1/4 bias) nt3881d com1 com8 seg1 seg40 lcd panel
nt3881d 19 v2.4 (b) 5 x 10 font - 8 character x 1 line (1/11 duty cycle, 1/4 bias) nt3881d com1 com8 seg1 seg40 lcd panel com11 com9 (c) 5 x 8 font - 8 character x 2 lines (1/16 duty cycle, 1/5 bias) nt3881d com1 com8 seg1 seg40 lcd panel com16 com9
nt3881d 20 v2.4 (d) 5 x 8 font - 16 character x 1 line (1/16 duty cycle, 1/5 bias) nt3881d com1 com8 seg1 seg40 lcd panel com16 com9
nt3881d 21 v2.4 (3) bias power connection nt3881d provides 1/4 or 1/5 bias for various duty cycle applica tions. the power division voltage is described in the following table. the connection of nt3881d, power supply, and resistors are also shown as follows: power division 1/8, 1/11 duty cycle - 1/4 bias 1/16 duty cycle - 1/5 bias v 1 v dd - 1/4 v lcd v dd - 1/5 v lcd v 2 v dd - 1/2 v lcd v dd - 2/5 v lcd v 3 v dd - 1/2 v lcd v dd - 3/5 v lcd v 4 v dd - 3/4 v lcd v dd - 4/5 v lcd v 5 v dd - v lcd v dd - v lcd nt3881d vdd v1 v2 v3 v4 v5 vr vee vdd r r r r v lcd vdd v1 v2 v3 v4 v5 vr vdd r r r r r v lcd vee nt3881d note: the resistance value depends on the lcd panel size.
nt3881d 22 v2.4 (4) lcd waveform a-type, 1/8 duty cycle, 1/4 bias 400 clocks 12345 812 1 frame v dd v 1 v2 (v 3) v 4 v 5 com1 a-type, 1/11 duty cycle, 1/4 bias 400 clocks 12345 11 1 2 1 frame v dd v 1 v2 (v 3) v 4 v 5 com1 a-type, 1/16 duty cycle, 1/5 bias 200 clocks 12345 16 1 2 1 frame v dd v 1 v2 (v 3) v 4 v 5 com1
nt3881d 23 v2.4 b-type, 1/8 duty cycle, 1/4 bias com1 v dd v1 v2 (v3) v4 v5 1234 9 400 clocks 1 frame 11.9ms 8 400 270k 1sec frame 1 = = 84.3hz 11.9ms 1 frequency frame = = 5678 16 2 1 b-type, 1/11 duty cycle, 1/4 bias com1 v dd v1 v2 (v3) v4 v5 1234 9 400 clocks 1 frame 16.3ms 11 400 270k 1sec 1frame = = 61.4hz 16.3ms 1 frequency frame = = 5678 22 2 1 10 11 12 21 b-type, 1/16 duty cycle, 1/5 bias com1 v dd v1 v2 v4 v5 1234 200 clocks 1 frame 11.9ms 16 200 270k 1sec 1frame = = 84.3hz 11.9ms 1 frequency frame = = 5 32 2 1 15 16 17 31 14 13 v3
nt3881d 24 v2.4 application circuit (for reference only) nt3881d lcd panel nt3882 c1 - c16 s1 - s40 d cl2 cl1 m v dd gnd v 1 v 2 v 3 v 4 v 5 dl1 cl2 cl1 m v dd gnd v 3 v 4 v 5 dr1 dl2 dr2 s1 - s40 s1 - s40 dr2 dl2 dr1 gnd v dd m cl1 cl2 dl1 r r r r r vr c c c c c gnd or other negative voltage sel1 fcs sel2 fcs sel1 sel2 v 2 v 6 v 1 v 3 v 4 v 5 v 2 v 6 v 1 nt3882
nt3881d 25 v2.4 bonding diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 81 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 (0, 0) nt3881dh y x 3175 m 3861 m 66 33 * substrate connect to v dd or keep floating * pad window area: 120m x 110m
nt3881d 26 v2.4 bonding dimensions unit: m pad no. designation x y pad no. designation x y 1 seg22 -1469 1743 41 db2 1469 -1707 2 seg21 -1469 1593 42 db3 1469 -1557 3 seg20 -1469 1443 43 db4 1469 -1407 4 seg19 -1469 1293 44 db5 1469 -1257 5 seg18 -1469 1143 45 db6 1469 -1107 6 seg17 -1469 993 46 db7 1469 -957 7 seg16 -1469 843 47 com1 1469 -807 8 seg15 -1469 693 48 com2 1469 -657 9 seg14 -1469 543 49 com3 1469 -507 10 seg13 -1469 393 50 com4 1469 -357 11 seg12 -1469 243 51 com5 1469 -207 12 seg11 -1469 93 52 com6 1469 -57 13 seg10 -1469 -57 53 com7 1469 93 14 seg9 -1469 -207 54 com8 1469 243 15 seg8 -1469 -357 55 com9 1469 393 16 seg7 -1469 -507 56 com10 1469 543 17 seg6 -1469 -657 57 com11 1469 693 18 seg5 -1469 -807 58 com12 1469 843 19 seg4 -1469 -957 59 com13 1469 993 20 seg3 -1469 -1107 60 com14 1469 1143 21 seg2 -1469 -1257 61 com15 1469 1292 22 seg1 -1469 -1407 62 com16 1469 1443 23 gnd -1469 -1557 63 seg40 1469 1593 24 osc1 -1469 -1707 64 seg39 1469 1743 25 osc2 -1183 -1862 65 seg38 1125 1862 26 v1 -1033 -1862 66 seg37 975 1862 27 v2 -883 -1862 67 seg36 825 1862 28 v3 -733 -1862 68 seg35 675 1862 29 v4 -583 -1862 69 seg34 525 1862 30 v5 -433 -1862 70 seg33 375 1862 31 cl1 -283 -1862 71 seg32 225 1862 32 cl2 -133 -1862 72 seg31 75 1862 33 vddb 76 -1691 73 seg30 -75 1862 34 m 268 -1862 74 seg29 -225 1862 35 d 418 -1862 75 seg28 -375 1862 36 rs 568 -1862 76 seg27 -525 1862 37 r/w 719 -1862 77 seg26 -675 1862 38 e 870 -1862 78 seg25 -825 1862 39 db0 1020 -1862 79 seg24 -975 1862 40 db1 1170 -1862 80 seg23 -1125 1862 81 vdda 76 -1816
nt3881d 27 v2.4 ordering information part no. package remarks nt3881dh-01 chip form refer to table 1 NT3881DF-01 80l qfp/b-type waveform refer to table 1 nt3881dh-02 chip form refer to table 2 nt3881df-02 80l qfp/b-type waveform refer to table 2
nt3881d 28 v2.4 package information qfp 80l outline dimensions unit: inches/mm a 1 a 2 a seating plane 1 24 b 25 40 41 64 65 80 e e g e g d see detail f detail f d h d h e d y l g d ~ ~ ~ l 1 c symbol dimensions in inches dimensions in mm a 0.130 max. 3.30 max. a 1 0.004 min. 0.10 min. a 2 0.1120.005 2.850.13 b 0.014 +0.004 0.35 +0.10 -0.002 -0.05 c 0.006 +0.004 0.15 +0.10 -0.002 -0.05 d 0.5510.005 14.000.13 e 0.7870.005 20.000.13 e 0.0310.006 0.800.15 g d 0.693 nom. 17.60 nom. g e 0.929 nom. 23.60 nom. h d 0.7400.012 18.800.31 h e 0.9760.012 24.790.31 l 0.0470.008 1.190.20 l 1 0.0950.008 2.410.20 y 0.006 max. 0.15 max. 0 ~ 12 0 ~ 12 notes: 1. dimensions d & e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only.
nt3881d 29 v2.4 product spec. change notice nt3881 specification revision history version content date 2.4 b-type waveform modified(pa ge 23 , document mistake corrected) apr.2002 2.3 pad 33 vddb,pad 81 vdda modified( page 5, 24) nov.2001 2.2 updated page 16. nov.2001 2.1 updated all diagrams. nov.1999 2.0 modified page1 - 1.0 new spec -

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